A B C D E F G L M O P Q R S T U W

A

add(String[], int) - Method in class org.vishia.fpga.testutil.TestSignalVerticalAdd

Contribution to output

addSignals(int, int, boolean) - Method in class org.vishia.fpga.testutil.TestSignalRecorder

This operation should be implemented to add the necessary signals to all existing lines which are created or cleaned in the overridden TestSignalRecorder.clean() and registered with TestSignalRecorder.registerLine(StringBuilder, String).

addSignals(int) - Method in class org.vishia.fpga.testutil.TestSignalRecorder

Simple for with bAdd = true, see #addSignals(int, boolean)

addSignals(int, int, boolean) - Method in class org.vishia.fpga.testutil.TestSignalRecorder.Empty

This operation is empty, does nothing, returns 0, no contribution for presentation.

addSignals(int, int, boolean) - Method in class org.vishia.fpga.testutil.TestSignalRecorder.Time

addSignals(int) - Method in class org.vishia.fpga.testutil.TestSignalRecorderSet

Add all signals to all recorders and equalizes the line length.

addSrc(TestSignalVerticalAdd) - Method in class org.vishia.fpga.testutil.TestSignalRecorderVertical

B

Bit_ifc - Interface in org.vishia.fpga.stdmodules

This is a very common interface only for one bit for any usage.

C

cc - Variable in class org.vishia.fpga.testutil.CheckOper.CharMinMax

CharMinMax(char, int, int) - Constructor for class org.vishia.fpga.testutil.CheckOper.CharMinMax

checkDbg(boolean) - Static method in class org.vishia.fpga.Fpga

checkLen(StringBuilder, int) - Static method in class org.vishia.fpga.testutil.TestSignalRecorder

This operation can be used to decide whether the StringBuilder has place for a new longer information, for example a bus value (hexa).

CheckOper - Class in org.vishia.fpga.testutil

CheckOper() - Constructor for class org.vishia.fpga.testutil.CheckOper

CheckOper.CharMinMax - Class in org.vishia.fpga.testutil

Helper class for check.

checkOutput(CharSequence, int, CheckOper.CharMinMax[]) - Static method in class org.vishia.fpga.testutil.CheckOper

checkTime(int, int, int) - Static method in class org.vishia.fpga.Fpga

Check the time.

checkVector(Class<?>, String, int) - Static method in class org.vishia.fpga.Fpga

Checks the size of a vector adequate to its annotation

clean() - Method in class org.vishia.fpga.testutil.TestSignalRecorder

This operation should be overridden in a kind that all buffers should be created and reseted using the TestSignalRecorder.registerLine(StringBuilder, String) operation.

clean() - Method in class org.vishia.fpga.testutil.TestSignalRecorderSet

Cleans all buffers in the recorders.

close() - Method in class org.vishia.fpga.testutil.TestSignalRecorderVertical

concatbits(int, int, int) - Static method in class org.vishia.fpga.Fpga

Concatenate two bit vectors

connect() - Method in class org.vishia.fpga.testutil.TestSignalRecorderVertical

D

d_q - Variable in class org.vishia.fpga.stdmodules.Reset

dst - Variable in class org.vishia.fpga.testutil.StateStoreFpga

E

Empty(String) - Constructor for class org.vishia.fpga.testutil.TestSignalRecorder.Empty

ctor

empty - Static variable in class org.vishia.fpga.testutil.TestSignalRecorderVertical

endSignals(int) - Method in class org.vishia.fpga.testutil.TestSignalRecorder

This operation fills all registered StringBuilder to the same length.

F

format - Variable in class org.vishia.fpga.testutil.TestSignalRecorder.Time

Fpga - Class in org.vishia.fpga

This class contains hardware related opeations for FPGA simulation which are also accepted by the Java2Vhdl translator.

Fpga() - Constructor for class org.vishia.fpga.Fpga

Fpga.BITVECTOR - Annotation Type in org.vishia.fpga

Defines an numeric variable in VHDL as BIT_VECTOR( DOWNTO 0) This allows only specific routines in this class or assignments.

Fpga.ClockedInput - Annotation Type in org.vishia.fpga

Defines that an input pin of the Fpga or of an module should be clocked immediately.

Fpga.GetterVhdl - Annotation Type in org.vishia.fpga

Defines that an Operation is existing in the module class to access data from RECORD instance (associated to a PROCESS).

Fpga.IfcAccess - Annotation Type in org.vishia.fpga

Defines a sub module in another module which is only responsible to implement an interface as access point to the containing module.

Fpga.STDVECTOR - Annotation Type in org.vishia.fpga

Defines an numeric variable in VHDL as STD_LOGIC_VECTOR( DOWNTO 0) This is necessary if numeric operations are done.

Fpga.VHDL_PROCESS - Annotation Type in org.vishia.fpga

Defines an numeric variable in VHDL as STD_LOGIC_VECTOR( DOWNTO 0) This is necessary if numeric operations are done.

FpgaModule_ifc - Interface in org.vishia.fpga

G

getBit(int, int) - Static method in class org.vishia.fpga.Fpga

Gets one bit from a vector.

getBit() - Method in interface org.vishia.fpga.stdmodules.Bit_ifc

getBits(int, int, int) - Static method in class org.vishia.fpga.Fpga

Returns in VHDL vector(6 DOWNTO 2) if msp=6 and lsb=2.

getBitsShL(int, int, boolean) - Static method in class org.vishia.fpga.Fpga

Shifts a vector 1 to left and replaces the bit 0 with low value.

getBitsShR(boolean, int, int) - Static method in class org.vishia.fpga.Fpga

Shifts a vector 1 to right and replaces the ms bit with high value.

getLine(String) - Method in class org.vishia.fpga.testutil.TestSignalRecorder

getLine(String) - Method in class org.vishia.fpga.testutil.TestSignalRecorderSet

L

lenClean - Static variable in class org.vishia.fpga.testutil.TestSignalRecorder

The length of the title of a line, after clean.

lenCurr - Variable in class org.vishia.fpga.testutil.TestSignalRecorderSet

lineSep - Variable in class org.vishia.fpga.testutil.TestSignalRecorder.Empty

M

max - Variable in class org.vishia.fpga.testutil.CheckOper.CharMinMax

measTime(int[], int, int) - Static method in class org.vishia.fpga.Fpga

min - Variable in class org.vishia.fpga.testutil.CheckOper.CharMinMax

moduleName - Variable in class org.vishia.fpga.testutil.TestSignalRecorder

Registered module name to build the line title.

O

open(File) - Method in class org.vishia.fpga.testutil.TestSignalRecorderVertical

org.vishia.fpga - package org.vishia.fpga

org.vishia.fpga.stdmodules - package org.vishia.fpga.stdmodules

org.vishia.fpga.testutil - package org.vishia.fpga.testutil

output(Appendable) - Method in class org.vishia.fpga.testutil.TestSignalRecorder.Empty

output(Appendable) - Method in class org.vishia.fpga.testutil.TestSignalRecorder

This operation outputs all lines.

output(Appendable) - Method in class org.vishia.fpga.testutil.TestSignalRecorderSet

Outputs the lines of all registered TestSignalRecorderSet.registerRecorder(TestSignalRecorder).

P

pos - Variable in class org.vishia.fpga.testutil.TestSignalRecorder

posNum - Variable in class org.vishia.fpga.testutil.TestSignalRecorder.Time

Q

q - Variable in class org.vishia.fpga.stdmodules.Reset

Q() - Constructor for class org.vishia.fpga.stdmodules.Reset.Q

Q(int, Reset.Q, Reset.Ref) - Constructor for class org.vishia.fpga.stdmodules.Reset.Q

q - Variable in class org.vishia.fpga.stdmodules.Reset.Store

R

recs - Variable in class org.vishia.fpga.testutil.TestSignalRecorderSet

ref - Variable in class org.vishia.fpga.stdmodules.Reset

Ref(Reset_Inpin_ifc) - Constructor for class org.vishia.fpga.stdmodules.Reset.Ref

registerLine(StringBuilder, String) - Method in class org.vishia.fpga.testutil.TestSignalRecorder

Helper operation to resets one line.

registerLines() - Method in class org.vishia.fpga.testutil.TestSignalRecorder.Empty

registerLines() - Method in class org.vishia.fpga.testutil.TestSignalRecorder

registerLines() - Method in class org.vishia.fpga.testutil.TestSignalRecorder.Time

registerRecorder(TestSignalRecorder) - Method in class org.vishia.fpga.testutil.TestSignalRecorderSet

Add one recorder (usual inside a module) to this set.

res - Variable in class org.vishia.fpga.stdmodules.Reset.Q

This is the variable of the record accessed from outside, but access via interface.

Reset - Class in org.vishia.fpga.stdmodules

Reset(Reset_Inpin_ifc) - Constructor for class org.vishia.fpga.stdmodules.Reset

Module constructor with public access to instantiate.

reset(int, int) - Method in class org.vishia.fpga.stdmodules.Reset

reset(int, int) - Method in interface org.vishia.fpga.stdmodules.Reset_ifc

Returns true for reset. false for normal operation.

Reset.Q - Class in org.vishia.fpga.stdmodules

Inner PROCESS class builds a TYPEDEF RECORD in VHDL and a PROCESS for each (usual one) instance.

Reset.Ref - Class in org.vishia.fpga.stdmodules

Reset.Store - Class in org.vishia.fpga.stdmodules

Stores the state for special tests.

Reset_ifc - Interface in org.vishia.fpga.stdmodules

Reset_Inpin_ifc - Interface in org.vishia.fpga.stdmodules

reset_Pin() - Method in interface org.vishia.fpga.stdmodules.Reset_Inpin_ifc

Access to an FPGA input pin for reset.

resetCount - Variable in class org.vishia.fpga.stdmodules.Reset.Q

resetInp - Variable in class org.vishia.fpga.stdmodules.Reset.Ref

restore() - Method in class org.vishia.fpga.stdmodules.Reset.Store

Restore the state to the same module, which is used on creation.

restore() - Method in class org.vishia.fpga.testutil.StateStoreFpga

The implementing operation should restore the appropriate states of the module.

S

sbs - Variable in class org.vishia.fpga.testutil.TestSignalRecorder

sbTime - Variable in class org.vishia.fpga.testutil.TestSignalRecorder.Time

setBit(int, int, boolean) - Static method in class org.vishia.fpga.Fpga

Gets one bit from a vector.

setBits(int, int, int, int) - Static method in class org.vishia.fpga.Fpga

Replaces the dedicated bits with value.

sLine - Variable in class org.vishia.fpga.testutil.TestSignalRecorderVertical

sOut - Variable in class org.vishia.fpga.testutil.TestSignalRecorderVertical

srcList - Variable in class org.vishia.fpga.testutil.TestSignalRecorderVertical

StateStoreFpga<FpgaModule> - Class in org.vishia.fpga.testutil

This is the abstraction of Store classes.

StateStoreFpga(int, FpgaModule) - Constructor for class org.vishia.fpga.testutil.StateStoreFpga

The super constructor.

step(int) - Method in interface org.vishia.fpga.FpgaModule_ifc

step(int) - Method in class org.vishia.fpga.stdmodules.Reset

Store(int, Reset) - Constructor for class org.vishia.fpga.stdmodules.Reset.Store

Creates a Store instance, which refers the data from the Reset.q instance, it is the PROCESS data, able to call after a defined simulation procedure, to resume later exact from this state.

sVersion - Static variable in class org.vishia.fpga.Fpga

Version, history and license.

sVersion - Static variable in interface org.vishia.fpga.FpgaModule_ifc

Version, history and license.

sVersion - Static variable in class org.vishia.fpga.testutil.StateStoreFpga

Version, history and license.

T

TestSignalRecorder - Class in org.vishia.fpga.testutil

A base for a test signal recorder for horizontal time deterministic presentation of states.

TestSignalRecorder(String) - Constructor for class org.vishia.fpga.testutil.TestSignalRecorder

Each module with several output lines need an instance of this class.

TestSignalRecorder.Empty - Class in org.vishia.fpga.testutil

With this class a member of TestSignalRecorderSet can be built which produces a separation line.

TestSignalRecorder.Time - Class in org.vishia.fpga.testutil

TestSignalRecorderSet - Class in org.vishia.fpga.testutil

This is a container class for some TestSignalRecorder for horizontal test signal outputs.

TestSignalRecorderSet() - Constructor for class org.vishia.fpga.testutil.TestSignalRecorderSet

TestSignalRecorderVertical - Class in org.vishia.fpga.testutil

TestSignalRecorderVertical() - Constructor for class org.vishia.fpga.testutil.TestSignalRecorderVertical

TestSignalVerticalAdd - Class in org.vishia.fpga.testutil

TestSignalVerticalAdd() - Constructor for class org.vishia.fpga.testutil.TestSignalVerticalAdd

time - Variable in class org.vishia.fpga.stdmodules.Reset.Q

time - Variable in class org.vishia.fpga.testutil.StateStoreFpga

The current time stamp for the storing the state.

Time(String, int) - Constructor for class org.vishia.fpga.testutil.TestSignalRecorder.Time

time0 - Variable in class org.vishia.fpga.testutil.TestSignalRecorder.Time

timeStep - Variable in class org.vishia.fpga.testutil.TestSignalRecorder.Time

timeStep10 - Variable in class org.vishia.fpga.testutil.TestSignalRecorder.Time

timeStep5 - Variable in class org.vishia.fpga.testutil.TestSignalRecorder.Time

U

update() - Method in interface org.vishia.fpga.FpgaModule_ifc

update() - Method in class org.vishia.fpga.stdmodules.Reset

W

wr - Variable in class org.vishia.fpga.testutil.TestSignalRecorderVertical

write(int) - Method in class org.vishia.fpga.testutil.TestSignalRecorderVertical

A B C D E F G L M O P Q R S T U W